As is known, there is a demand for integrated devices incorporating in the same chip both a power stage (e.g., MOSFET power transistor, VDMOS) and the relative low-voltage drive circuits (e.g., comprising NMOS and PMOS transistors).
In some applications, the drive voltage of such devices may oscillate between two fairly high values (a few tens of volts) symmetrical with respect to the reference voltage (ground), which causes a problem in maintaining isolation between the drive circuit components and the power stage.
For a clearer understanding of the problem, refer to FIG. 1 showing an integrated device 1 comprising a power transistor (VDMOS) 2 and relative control circuitry (drive stage) 3. The drain terminal D of VDMOS 2 presents voltage V.sub.D, its source terminal S is grounded, its gate terminal G is driven by drive stage 3, and 4 indicates the relative parasitic diode. Power transistor 2 presents N.sup.+ -type source and drain regions. The drive stage 3 shows only an input terminal 5 supplied with input voltage V.sub.IN (oscillating drive voltage); an N.sup.+ -type region (input region) 6 is connected to input terminal 5 (and forming part of any component, e.g., constituting the collector region of an NPN transistor); and a P.sup.+ -type isolating region 7 surrounds and isolates region 6 from the substrate connected to or constituting the drain region of VDMOS 2. FIG. 1 also shows two parasitic NPN transistors 8, 9 and a parasitic PNP transistor 10, which are associated with the FIG. 1 structure as shown more clearly in the example integrated circuit implementation in FIG. 2.
FIG. 2 shows a cross section of a silicon wafer including an N.sup.+ -type substrate (substrate region) 11, and an N.sup.- -type epitaxial layer 12 forming with substrate 11 the drain region of VDMOS 2. To the left is shown VDMOS 2 including N.sup.+ -type source regions (reference potential region) 15, polysilicon gate regions 16 embedded in insulating layer 17, and metal source line 18. To the right is shown a CMOS component (including in known manner an N-channel and P-channel MOS transistors) formed in a well comprising a P-type buried layer 20. P.sup.+ -type regions 22, 23 provide for isolating the various components. More specifically, region 22 encloses and isolates the low-voltage components, corresponds to region 7 in FIG. 1, and separates an N.sup.- well layer 24 and a P-well layer 25 over buried layer 20. N.sup.- well layer 24 presents an N.sup.+ -type region 29; and P.sup.+ -type regions 26 constituting the drain and source of the NMOS transistor are located beneath gate region 27 embedded in dielectric layer 28. P-well layer 25 presents N.sup.+ -type regions 30 constituting the drain and source of the NMOS transistor and located beneath gate region 31 embedded in dielectric layer 32. Metal lines 33 contact the NMOS and PMOS transistor regions in a well-known manner.
In the circuit structure of FIG. 2, the N.sup.+ -type type regions (e.g., regions 29, 30) form parasitic diodes together with isolating region 22, and, together also with epitaxial layer 12 and substrate 11, form parasitic NPN transistors 8 and 9 in FIG. 1. The bases of transistors 8, 9 are connected to the isolating region 7; the emitter of transistor 8 and the collector of transistor 9 are connected to N.sup.+ -type region 6; and the collector of transistor 8 and the emitter of transistor 9 are connected to the drain region of VDMOS 2. Moreover, region 23 (connected electrically to source region 15 by metal line 18) and regions 12 and 22 form the parasitic transistor 10 in FIG. 1. The parasitic transistor has its collector connected to isolating region 7, its base connected to drain terminal D, and its emitter connected to source terminal S of VDMOS 2.
With such a structure, isolating region 7 (22) cannot be grounded when drive voltage V.sub.IN is negative; in that case, if one of regions 29 or 30 is connected to voltage V.sub.IN, the aforementioned diode (formed by said region 29 or 30 and isolating region 22) would be biased directly, and the transistor (8 in FIG. 1) formed by said regions and epitaxial layer 12 would turn on or operate to interfere with proper operation of the circuit 1.
Similarly, isolating region 22 cannot be connected directly to input voltage V.sub.IN in that, when voltage V.sub.IN is positive, the parasitic diode formed by isolating region 22 and epitaxial layer 12 would be biased directly, and the parasitic transistor (9 in FIG. 1) formed by the parasitic diode and the N.sup.+ region connected to voltage V.sub.IN would be turned on, due also to the current injected by transistor 10 which is turned on when voltage V.sub.D is negative.
If isolating region 22 were to be grounded, parasitic transistor 9 would also be turned on with a negative voltage V.sub.D.